The present invention relates to semiconductor integrated circuitry and to a technology for manufacturing semiconductor integrated circuitry; and more particularly, the present invention relates to a technology effectively applicable for realizing higher integration and higher performance of a DRAM (Dynamic Random Access Memory) or an electrically reloadable nonvolatile memory, or for a highly integrated semiconductor circuit provided with a logic circuit and a DRAM or an electrically reloadable nonvolatile memory.
There is a DRAM used as a semiconductor memory representing a large capacity memory. The memory capacity of this DRAM is increasing more and more, and, under the circumstances, it has become necessary to reduce the area occupied by the memory cells to improve the degree of integration of the DRAM.
However, the storage capacity of an information storing capacity element (capacitor) in DRAM memory cells must be fixed to a certain value regardless of the generation when in taking the DRAM operation margin, software errors, etc. into consideration. Generally, it is known that the storage capacity cannot be reduced proportionally.
This is why there is now under development a capacitor structure that can secure a storage capacity necessary in a limited small occupation area. As such a capacitor structure, for example, there has been adopted a three-dimensional capacitor, such as a so-called stacked capacitor composed of two-layer electrodes composed of polysilicon, etc. and stacked via a capacity insulating film.
A stacked capacitor is generally composed of capacitor electrodes disposed in the upper layer of a memory cell selecting MISFET (Metal Insulator Semiconductor Field Effect Transistor). In this case, a small occupied area can secure a large storage capacity, as well as only a small storage capacity, as needed.
As such a stacked capacitor structure, for example, there are a so-called capacitor over bit-line (hereafter, to be abbreviated as COB) structure, in which a capacitor is disposed over the bit-line, and a capacitor under bit-line (hereafter, to be abbreviated as CUB) structure, in which a capacitor is disposed under the bit-line.
In a DRAM having such a COB/CUB structure, capacitor connecting holes must be formed so that a conductor film or a bit-line in each capacitor connecting hole is not short-circuited with a word-line. Thus, the interval between adjacent word-lines must be widened to cope with connecting hole positioning failures. And, this hinders improvement of the degree of integration of elements, as well as a reduction of the chip sizes. In order to realize high integration, therefore, high technology of positioning and alignment, as well as process management, are needed.
In order to solve these problems and meet certain requirements, there is proposed a technology for forming capacitor connecting holes and bit-line connecting holes by etching in a self-matching manner with respect to the word-lines by covering the top and side surfaces of the word-lines using an insulating material different in type from an interlaminar insulating film, such as a nitride film, etc.
In the case of such a technology, when capacitor connecting holes and bit-line connecting holes are formed by etching, it is possible to prevent the word-lines from being exposed from the connecting holes, even when the connecting holes overlap the word-lines, since the nitride film around the word-lines functions as an etching stopper. Thus, the connecting holes can be formed properly.
The technology for forming capacitor connecting holes and bit-line connecting holes in a self-matching manner with respect to the word-lines is disclosed in the official report of Unexamined Published Japanese Patent Application No. 9-55479.
Under the circumstances, the present inventor has examined the technology for forming the capacitor connecting holes and bit-line connecting holes in a self-matching manner with respect to the word-lines. The following technologies are not well-known, but have been examined by the present inventor. An outline of those technologies will be described below.
The DRAM described above is formed in the following process flow. At first, a conductor layer is formed on a semiconductor substrate via a gate insulating film. On the conductor film there is deposited a first nitride film. Then, the first nitride film and the conductor film are patterned using the same mask to form gate electrodes of the memory cell selecting MISFET and gate electrodes of the peripheral circuit MISFET. At this time, the gate electrodes of plural memory cells disposed in the row direction of the memory cell array are formed unitarily and function as a DRAM word line. Next, a low density semiconductor area is formed for the memory cell selecting MISFET and the peripheral circuit MISFET, respectively, in a self-matching manner with respect to the memory cell selecting MISFET and the peripheral circuit MISFET, respectively. Then, a second nitride film is deposited on the semiconductor substrate and anisotropic etching is carried out to form nitride film side wall spacers on side walls of the gate electrodes of both the memory cell selecting MISFET and the peripheral circuit MISFET. Then, a high density semiconductor area is formed for the peripheral circuit MISFET in a self-matching manner with respect to the side wall spacers. Thereafter, on the semiconductor substrate there is deposited an interlaminar insulating film composed of an oxide film, and bit-line and capacitor connecting holes are opened in the memory cell area in a self-matching manner with respect to word-lines. This process for opening the bit-line and capacitor connecting holes in this interlaminar insulating film is performed on conditions to increase the etching selection ratio of the nitride film composing side walls to the oxide film composing the interlaminar insulating film, so that the bit-line and capacitor connecting holes can be formed without exposing the word-lines.
On the other hand, in order to improve the degree of integration of the DRAM memory cells, the interval between word-lines must be minimized. When the second nitride film is deposited on the word-lines disposed at minimized intervals up to a specified film thickness or more, every space between word-lines in the memory cell area is filled completely with the second nitride film, so that the surface of the semiconductor substrate is not exposed even after anisotropic etching is carried out for the nitride film to form side wall spacers. Otherwise, a problem that the exposed area is very small and the contact resistance generated between the exposed area and each bit-line or capacitor electrode is increased significantly arises.
In addition, side wall spacers formed on side walls of the gate electrodes of both the memory cell selecting MISFET and the peripheral circuit MISFET determine the length of the low density semiconductor area of the peripheral circuit MISFET having an LDD structure. And, when this side wall spacer is reduced in width, problems arise in that the short channeling effect of the peripheral circuit MISFET becomes remarkable and the punched-through dielectric strength between source and drain is lowered. This is why the second nitride film for forming side wall spacers must have a thickness greater than a specified value.
In other words, in order to secure a specified performance of a MISFET, the LDD structure must be optimized. When the DRAM memory cell selecting MISFET is divided finely to reduce the width of the side wall spacer, the side wall spacer width must be greater than a specified value to prevent the high density semiconductor area of the peripheral circuit MISFET from being distributed over the low density semiconductor area. This means that the width of each side wall spacer has a lower limit.
On the other hand, when the memory array is divided finely, the interval between gate electrodes, that is, the interval between adjacent memory cell selecting MISFETs is narrowed accordingly. Thus, every portion to be connected in a self-matching manner is also reduced in width. When such a connecting area is narrowed, the contact resistance in the area is also increased significantly. Thus, the side wall spacer must be minimized in width. Such a requirement conflicts with a requirement for optimizing the LDD structure. And, in the worst case, when the LDD structure is optimized, adjacent side wall spacers are overlapped in the memory array area so that self-matching connections are disabled.
Under the circumstances, it is an object of the present invention to provide semiconductor integrated circuit technology for dividing DRAM memory cells finely so as to be more highly integrated and to make the operation faster in the semiconductor integrated circuitry provided with a DRAM.
It is another object of the present invention to provide a semiconductor integrated circuit technology for dividing memory cells finely so as to be more highly integrated and make the operation faster in the semiconductor integrated circuitry provided with a DRAM and an electrically reloadable nonvolatile memory.
It is still another object of the present invention to provide a technology for realizing a high performance semiconductor integrated circuit having a DRAM which exhibits excellent refreshing characteristics.
It is still another object of the present invention to provide a technology for realizing a semiconductor integrated circuit that can prevent the element isolating area on the semiconductor substrate from over-etching when opening the connecting holes to improve the reliability of the semiconductor integrated circuitry.
It is still another object of the present invention to provide a technology for simplifying the method of manufacturing a semiconductor integrated circuit provided with a DRAM and an electrically reloadable nonvolatile memory.
It is still another object of the present invention to provide a technology for realizing a semiconductor integrated circuit, which can divide DRAM cells finely so as to be more highly integrated and improve the reliability of the peripheral circuit MISFET.
It is still another object of the present invention to provide a technology for forming connecting holes in a self-matching manner even in a highly integrated DRAM memory cell area and to prevent the element isolating area at the bottom of each of the connecting holes from over-etching.
It is still another object of the present invention to provide a technology for improving the connecting hole treatment margin when the connecting holes are formed in a self-matching manner and for preventing the element isolating area at the bottom of each connecting hole from over-etching.
It is still another object of the present invention to provide a technology for suppressing an increase in the number of processes required when the connecting holes are formed in a self-matching manner and the element isolating area at the bottom of each connecting hole is prevented from over-etching.
It is still another object of the present invention to provide a technology for integrating a semiconductor integrated circuit more highly and for improving the refreshing characteristics of the DRAM and the transistor characteristics of the memory cell area.
The above and other objects and novel features of the present invention will fully appear from the description provided by this specification and from the accompanying drawings.
Of the various aspects of the present invention disclosed in this specification, representative ones will be summarized as follows.
(1) The semiconductor integrated circuit of the present invention comprises a first MISFET including gate electrodes formed on the main surface of a semiconductor substrate via a gate insulating film and a semiconductor area which is in contact with a channel area on the main surface of the semiconductor substrate under the gate electrodes; and a second MISFET including gate electrodes formed on the main surface of a semiconductor substrate via a gate insulating film and a low density semiconductor area in contact with a channel area on the main surface of the semiconductor substrate under the gate electrodes and a high density semiconductor area formed outside the low density semiconductor area, wherein a cap insulating film is formed on top of the first and second MISFET gate electrodes, first side walls composed of a first insulating film are formed on side surfaces of the second MISFET gate electrodes, and second side walls composed of a second insulating film, which is of a different material from that of the first insulating film, are formed outside the first side walls. Then, a conductor portion connecting the first MISFET semiconductor area to a member formed in the upper layer of the first MISFET is formed in a self-matching manner with respect to third side walls formed with the first insulating film, and the second MISFET high density semiconductor is formed in a self-matching manner with respect to the second side walls formed with the second insulating film.
According to the above-described semiconductor integrated circuitry, since the first and second insulating films are formed on side surfaces of the gate electrodes, the connecting portion connecting a member formed in the upper layer of the first MISFET is formed in a self-matching manner with respect to the third side walls formed with the first insulating film, and the second MISFET high density semiconductor area is formed in a self-matching manner with respect to the second side walls formed with the second insulating film, the degree of integration and the performance of the semiconductor integrated circuitry can be improved significantly.
In other words, the third side walls formed with the first insulating film can secure the self-matching properties of the conductor portion used to connect the first MISFET semiconductor area to the member formed in the upper layer of the first MISFET, while the second side walls formed with the second insulating film can optimize the position of the high density semiconductor area necessary to form a so-called LDD of the second MISFET, so that the second MISFET can maintain a high performance satisfactorily. In other words, the first insulating film may be, for example, a silicon nitride film, which is a material having an etching selection ratio for the silicon oxide film, which is a material of general interlaminar insulating films, and the second insulating film may be a silicon oxide film that can block implanted ions necessary for forming an LDD. And, the second insulating film does not disturb self-matching connection for the first MISFET. On the other hand, the first and second insulating films can function as effective spacers for forming the LDD. Consequently, as for the first insulating film, there is no need to take any space into consideration when designing an LDD structure and it is only necessary to make the second insulating film thick enough to realize the self-matching connection. Thus, the second insulating film can be reduced in thickness to allow the first MISFET to be integrated more highly. On the other hand, as for the second insulating film, there is no need to take the interval between gate electrode wirings in the first MISFET forming area into consideration. Thus, side wall spacers can be formed with a film thickness sufficient to maintain the second MISFET performance, so that the performance of the second MISFET can be improved more significantly.
The first insulating film can be used for the first and third side wall spacers composed of a silicon nitride film formed on side surfaces of the gate electrodes, and the second insulating film can be used for the second side wall spacers composed of a silicon oxide film formed on side surfaces of the gate electrodes with a first side wall spacer disposed therebetween, respectively.
The first insulating film can be a silicon nitride film formed on the semiconductor substrate including side surfaces of the gate electrodes, and the second insulating film can be used for side wall spacers composed of a silicon oxide film formed on side surfaces of the gate electrodes with a silicon nitride film disposed therebetween, respectively. In such a case, when the connecting holes are opened for connecting each MISFET, the etching process can be divided into a first etching process for etching a silicon nitride film and a second etching process for etching a silicon nitride film, so that a silicon nitride film can be used as an etching stopper for the first etching process. When the etching process is divided into two stages in such a way, connecting holes can be opened surely in the first etching, and over-etching can be prevented in the second etching process.
Furthermore, the semiconductor integrated circuitry of the present invention includes an N channel MISFET and a P channel MISFET in the second MISFET and can have a C (Complementary) MISFET structure. According to such semiconductor integrated circuitry, a higher performance and a lower power consumption can be realized due to the MISFET structure, so that it is possible to form not only DRAM peripheral circuits, but also logic circuits using the second MISFET. Thus, the semiconductor integrated circuitry can have memory and logic circuits together.
(2) The semiconductor integrated circuitry of the present invention is as described in section (1), and the first MISFET is a DRAM selecting MISFET disposed in the DRAM cell memory array area and the member formed in the upper layer of the first MISFET is a DRAM storage capacitor or a bit line.
According to the semiconductor integrated circuitry, the DRAM memory cell integration degree is improved and the performance of the peripheral circuits formed with the second MISFET is improved, so that it is possible to realize a high speed high performance DRAM integrated circuit.
In addition, phosphorus is doped in the selecting MISFET semiconductor area as an impurity and at least arsenic can be doped in the low density or high density semiconductor area of the N channel MISFET of the second MISFET. In addition, the N channel MISFET can include the first N channel MISFET and a second N channel MISFET, and the first N channel MISFET can include an arsenic doped low density semiconductor area, a phosphorus doped high density semiconductor area, and a arsenic doped high density semiconductor area. In addition, the first N channel MISFET can include a semiconductor in which boron is doped in an area in contact with the high density semiconductor area under the low density semiconductor area, and the second N channel MISFET does not include any boron doped semiconductor area.
When phosphorus is doped in the selecting MISFET semiconductor area as an impurity in such a way, the selecting MISFET dielectric strength can be improved and the leakage current between the source and drain can be reduced to improve the refreshing characteristics of the DRAM. Furthermore, when arsenic is doped in both low density and high density semiconductor areas of the first N channel MISFET, the first N channel MISFET channel length can be shortened, and when phosphorus is doped in the low density semiconductor area and arsenic is doped in the high density semiconductor area of the second N channel MISFET, the dielectric strength of the second N channel MISFET can be improved significantly. Furthermore, since a boron-doped semiconductor area is formed in the first N channel MISFET so as to function as a punched-through stopper, the channel length can further be shortened, and since no punched-through stopper is provided in the second N channel MISFET, the dielectric strength of the MISFET can further be improved.
Furthermore, it can be expected that no silicide layer is formed on the surface of the selecting MISFET semiconductor area and that a silicide layer is formed on the surface of the high density semiconductor area. Since no silicide layer is formed on the surface of the selecting MISFET semiconductor area, the leakage between channels can be suppressed to form a DRAM having excellent refreshing characteristics, and since a silicide layer is formed on the surface of the high density semiconductor area, the resistance in the second MISFET connecting holes and the sheet resistance of the semiconductor area can be reduced to make the MISFET operation faster and improve the performance of the semiconductor integrated circuitry.
The selecting MISFET gate insulating film can be thicker than the second MISFET gate insulating film. Since the second MISFET gate insulating film is thinned in this way, the second MISFET channel length can be shortened, and since the selecting MISFET gate insulating film is thickened in this way, the dielectric strength of the MISFET can be improved to form a DRAM having excellent refreshing characteristics. Furthermore, when the second MISFET channel length is shortened, the semiconductor integrated circuitry can increase the MISFET driving current and enable its performance to be higher and its operation to be faster.
(3) The semiconductor integrated circuitry of the present invention is as described in section (1), and the first MISFET gate can be a floating gate type MISFET, where the insulating film is a tunnel insulating film. The floating gate type MISFET is disposed in the memory array area for nonvolatile memory cells including the gate electrodes, floating gates, and control gates formed on the floating electrodes via an insulating film.
According to this semiconductor integrated circuitry, just like the DRAM described in section (2), the memory array area for the nonvolatile memory cells can be highly integrated and the performance of the peripheral circuit MISFET of the nonvolatile memory composed of the second MISFET can be improved significantly.
The second MISFET gate insulating film can be thicker than the first MISFET gate insulating film. Since the second MISFET gate insulating film is thickened, the dielectric strength of the peripheral circuit MISFET of the nonvolatile memory driven with a general high voltage can be increased more significantly.
(4) The semiconductor integrated circuitry of the present invention includes both the DRAM and the nonvolatile memory as described in sections (2) and (3). In other words, the first MISFET includes both the selecting MISFET and the floating gate type MISFET.
According to this semiconductor integrated circuitry, the DRAM and the nonvolatile memory array area can be highly integrated and the peripheral or logic circuit area can also be highly integrated.
The DRAM bit line and the wiring formed in the upper layer of the floating gate type MISFET can be formed in the same process. Consequently, the number of processes can be reduced.
The insulating films of the selecting MISFET, the floating gate type MISFET, the peripheral circuit or logic circuit MISFET that drives the DRAM, and the peripheral circuit MISFET that drives the floating gate type MISFET differ in thickness from each other. And, it can be expected that the gate insulating film of the peripheral circuit MISFET that drives the floating gate type MISFET is thicker than that of the floating gate type MISFET, and the gate insulating film of the floating gate type MISFET is thicker than that of the selecting MISFET, and the selecting MISFET gate insulating film is thicker than the gate insulating film of the peripheral circuit or logic circuit MISFET that drives the DRAM. Consequently, the gate insulating films of the selecting MISFET, the floating gate type MISFET, and the peripheral circuit or logic circuit MISFET that drives the DRAM, and the peripheral circuit MISFET that drives the floating gate type MISFET, can be optimized in thickness for each MISFET.
In the semiconductor integrated circuitry as described in any of sections (1) to (4), it can be expected that a silicon nitride film is formed in the second MISFET formed area so as to cover the second MISFET and the semiconductor substrate.
According to this semiconductor integrated circuitry, since a silicon nitride film is formed in the peripheral circuit or logic circuit area on the semiconductor substrate, the element isolating area can be prevented from over-etching even when connecting holes are formed in the element isolating area on the semiconductor substrate. Thus, no leakage occurs from between elements. And, accordingly, the semiconductor integrated circuitry can prevent generation of defects, thereby improving both reliability and performance.
(5) The method of manufacturing the semiconductor integrated circuitry of the present invention includes processes: (a) for forming a gate insulating film on the main surface of a semiconductor substrate; (b) for forming gate electrodes and a cap insulating film on the gate insulating film; (c) for forming a low density semiconductor area of the first and second MISFETs in a self-matching manner, respectively, with respect to the gate electrodes; (d) for forming the first side wall spacers on side surfaces of each of the gate electrodes; (e) for forming the second side wall spacers outside the first side wall spacers; (f) for forming a high density semiconductor area in a self-matching manner with respect to the second side wall spacers of the second MISFET; (g) for depositing an interlaminar insulating film composed a silicon oxide film all over the semiconductor substrate; (h) for etching the interlaminar insulating film and the second side wall spacers and opening the connecting holes in a self-matching manner with respect to the first side wall spacers of the first MISFET; and (i) for forming a conductor portion in each of the connecting holes.
Furthermore, the method of manufacturing the semiconductor integrated circuitry of the present invention includes processes: (a) for forming a gate insulating film on the main surface of a semiconductor substrate; (b) for forming gate electrodes and a cap insulating film on the gate insulating film; (c) for forming a low density semiconductor area of the first and second MISFETs in a self-matching manner, respectively, with respect to the gate electrodes; (d) for depositing a silicon nitride film all over the surface of the semiconductor substrate including the side surfaces of each of the gate electrodes; (e) for forming side wall spacers on side surfaces of the gate electrodes with a silicon nitride film formed therebetween; (f) for forming a high density semiconductor area in a self-matching manner with respect to the side wall spacers of the second MISFET; (g) for depositing an interlaminar insulating film composed of a silicon oxide film all over the semiconductor substrate; (h) for etching the interlaminar insulating film and the side wall spacers to form openings in a self-matching manner with respect to the silicon nitride film, and etching the silicon nitride film at the bottom of each opening to open the connecting holes; and (i) for forming a conductor portion in each of the connecting holes.
According to the semiconductor integrated circuitry, it is possible to form a semiconductor integrated circuitry as described in section (1).
(6) In the process (c), the manufacturing method of the present invention can implant phosphorus in the first MISFET semiconductor area and implant arsenic in at least one or more low density n-type semiconductor areas of the second MISFET. According to this manufacturing method, the dielectric strength of the first MISFET can be improved, and when arsenic is implanted in the low density semiconductor area of the second MISFET, the second MISFET channel length can be shortened.
Furthermore, in the process (a), both the first MISFET gate insulating film and the second MISFET gate insulating film can be formed in the same process. In such a case, the gate insulating film forming process can be shortened and simplified.
Furthermore, the process (a) for forming an insulating film can include a process for forming the first gate insulating film in an area where the first and second MISFETs are formed, a process for removing the first insulating film selectively from the area where the second MISFET is formed, and a process for forming the second insulating film in an area where the second MISFET is formed. When those additional processes are included in the process (a), since the first and second MISFET gate insulating films can be formed differently in thickness from each other, and after the first gate insulating film is formed, the second insulating film is formed, the second gate insulating film can be thinner than the first gate insulating film.
The method of manufacturing the semiconductor integrated circuitry according to the present invention is as described in section (5), and the gate insulating film can be a tunnel insulating film of the floating gate type MISFET composing a nonvolatile memory and the process for forming gate electrodes can include a process for forming the floating gate electrodes of the floating gate type MISFET and a process for forming the control gate electrodes of the floating gate type MISFET. According to the manufacturing method of the semiconductor integrated circuitry, it is possible to form a nonvolatile memory in which the memory array area can be highly integrated and the performance of the peripheral circuit area can be improved significantly.
(8) The method of manufacturing the semiconductor integrated circuitry according to the present invention is as described in sections (5) or (6), and prior to the process (a), there are included a process for forming the tunnel insulating film of the floating gate type MISFET composing a nonvolatile memory on the main surface of the semiconductor substrate and a process for forming the floating gate electrodes of the floating gate type MISFET on the tunnel insulating film.
According to the manufacturing method of the present invention, it is possible to manufacture a semiconductor integrated circuit provided with both a DRAM and a nonvolatile memory in which the memory array area is highly integrated and the performance of the peripheral circuit area is improved significantly.
The gate electrodes formed in the process (b) and the control gates of the floating gate type MISFET can be formed in the same process to simplify the process.
Furthermore, the tunnel insulating film can be thicker than the gate insulating film formed in the process (a).
(9) The method of manufacturing the semiconductor integrated circuitry is as described in sections (5) to (8), and prior to the process (g), there can be included a process for depositing the second silicon nitride film in the area where the second MISFET is formed, etching the interlaminar insulating film in the area where the conductor portion connecting the second MISFET to a member is formed in the upper layer of the second MISFET conditions determined so that an etching selection ratio can be taken for the second silicon nitride film to form openings, and furthermore etching the second silicon nitride film at the bottom of each opening to open connecting holes to form a conductor portion.
According to the manufacturing method of the present invention, since etching of the interlaminar insulating film is stopped by the second silicon nitride film, then the second silicon nitride film can be thinned much more than the interlaminar insulating film can be etched, over-etching will be sufficient if it is made up to xc2xd of the second silicon nitride film. And, even when connecting holes overlap on the element isolating area on the semiconductor substrate, the element isolating area can be prevented from over-etching. Consequently, a proper etching process margin can be secured, the element isolating function of the element isolating area can be kept, and the performance and reliability of the semiconductor integrated circuitry can be secured.
The second silicon nitride film and the silicon nitride film formed as the first insulating film can be formed in the same process.
Hereunder, the effects to be obtained by the representative aspects of the invention as set forth above will be described briefly.
(1) The present invention can provide semiconductor integrated circuitry technology for dividing the memory cells of a DRAM or a nonvolatile memory finely so as to be integrated more highly and to make the operation faster in a semiconductor integrated circuit provided with a DRAM or a nonvolatile memory.
(2) The present invention can provide semiconductor integrated circuitry technology for dividing memory cells finely so as to be integrated more highly and make the operation faster in a semiconductor integrated circuit provided with a DRAM or an electrically reloadable nonvolatile memory.
(3) It is possible to provide a technology for realizing a high performance semiconductor integrated circuit with excellent DRAM refreshing characteristics.
(4) It is possible to provide a technology for realizing a highly reliable semiconductor integrated circuit that can prevent an element isolating area on the semiconductor substrate from over-etching when connecting holes are opened.
(5) It is possible to simplify the manufacturing processes for a semiconductor integrated circuit provided with a DRAM and an electrically reloadable nonvolatile memory.